Analog to digital converters| RedEngine

Analog to digital conversion is the process of transforming the signal from the analog domain to the digital domain. This process could take place at baseband, as is the case of the direct conversion receivers, or at an intermediate frequency (IF) or low IF depending on the requirements and consequently on the receiver architecture pursued by the designers.

Why do we need analog to digital data conversion?

All the real-world signals are analog signals. And our computers work with digital data. Therefore, the processing of analog data using a microcontroller or microprocessor needed to be converted to digital form.

Some more advantages of data in digital form are

  • Digital data has a great advantage when storage is necessary. For example, music when converted to digital form can be stored more compactly and reproduced with greater accuracy and clarity than is possible when it is in analog form.
  • Noise (unwanted voltage fluctuations) does not affect digital data nearly as much as it does analog signals.

Different types of analog-to-digital converters

1. Dual Slope ADC

  • A dual-slope ADC(DS-ADC) integrates an unknown input voltage(Vin) for a fixed amount of time (Tint), then de-integrates(Tdeint) using a known reference voltage (Vref) for a variable amount of time.
  • The advantage of this architecture over the single-slope is that the final conversion result is insensitive to errors in the component values. That is, any error introduced by a component value during the integrated cycle will be canceled out during the de-integrate phase.

2. Flash ADC

  • An N-bit flash ADC consists of 2exponent N -1 parallel comparators that are all clocked simultaneously.

All the comparators simultaneously compare the input with their corresponding reference voltages. If the input voltage is larger than a reference voltage, then the corresponding comparator generates a logic output of 1(high); otherwise, the logic output is 0(low).

The outputs of the comparators connected between the low and high reference voltages give rise to a series of 1s transitioning to a series of 0s. This pattern is called a thermometer code. The thermometer-to-binary encoder generates the final binary output.

  • All comparators operate at one clock cycle making it ideal for high-speed application.
  • But as the number of bits increases, the number of comparators increases exponentially making area and power inefficient.

3. Subranging  and Two-step ADCs

  • Subranging and Two-step architecture was introduced as a solution to the problem of flash architecture.

In subranging or two-step ADC, a high-resolution conversion task is divided between two ADCs with lower resolution that operate sequentially.

The coarse ADC operates with a full-scale range and resolves the MSBs from the sampled input voltage. The DAC generates a quantized reference level according to the MSBs. Next, the DAC output is subtracted from the sampled input voltage, generating a residue voltage. Finally, the fine ADC in the second stage, operating with a subrange of the full-scale range, resolves the LSBs from the residue voltage.

  • Using this architecture reduces the number of comparators to large extent.
  • But it also has some drawbacks such as the second stage must wait for the first stage conversion and the residue generation, therefore there is inevitable latency in the final digital output.

Non-ideality of DAC can introduce errors in LSBs.

4. Successive Approximation Register ADCs

  1. Full analog-to-digital conversion in a SAR ADC is performed over multiple clock cycles. The reference voltage of the comparator is generated by a DAC that has a resolution equal to the SAR ADC resolution, and that is controlled by the digital SAR logic. The first clock cycle is generally dedicated to sampling the input. In the first cycle after the sampling, the DAC output is set to VFS/2, such that the comparator compares the sampled voltage with the middle reference level, resolving the first MSB. Depending on the comparator’s output after each comparison, the SAR logic sets the DAC input bits to generate the appropriate reference voltage for the next comparison. The process continues until the last bit is resolved.
  2. SAR ADCs are power efficient because they do not use large power-consuming components such as opamp.
  3. But, their conversion speed is limited due to the large number of conversion cycles required for a full analog-to-digital conversion.

5. Pipelined ADCs

  • Pipelined ADC architectures combine the concept of two-step analog-to-digital conversion with a pipelining technique to extend high-resolution operation to higher conversion rates. After sampling, the first stage starts to generate its corresponding output bits. It also generates the residue voltage and amplifies it to full-scale to be delivered to the next stage. This operation continuously occurs in all of the subsequent stages. While the current stage is converting a sample, the preceding stage is processing the next sample. The last few LSBs in the final stage of a pipelined ADC are generally resolved by a low-resolution flash ADC.
  • Its advantage is that the final digital output code is generated at the same conversion as that of one pipelined stage.

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